1. Field of the Invention
The present invention relates to a semiconductor device with a semiconductor chip including a semiconductor element, which is mounted in a package.
2. Description of the Related Art
In recent years, for power devices such as a device having a vertical MOSFET, miniaturization is required, and it is strongly desired to reduce electric resistance such as on-resistance. Along with an increase in capacity, it is necessary to reduce thermal resistance and efficiently release heat generated from chips to the outside.
A semiconductor device having this type of power device is generally structured as follows. A power element is formed in a semiconductor chip. The semiconductor chip includes first and second principal surfaces, on which electrodes are provided respectively. These electrodes are connected to lead frames. The semiconductor chip is disposed and sealed in a housing of resin.
In a semiconductor device described in U.S. Pat. No. 6,040,626, a gate electrode formed on the first principal surface of the semiconductor chip is connected to a first lead frame through a gate wire. A source electrode disposed on the first principal surface of the semiconductor chip is connected to a second lead frame through a top plate portion. A drain electrode disposed on the second principal surface of the semiconductor chip is connected to a third lead frame through a bottom plate portion. Such a top plate portion realizes reduction of on-resistance. The semiconductor chip, the gate wire, and part of the first to third lead frames are sealed in the housing.
In the above described semiconductor device, the source electrode, through which a large amount of current needs to flow, is connected to the top plate portion of the lead frame. Therefore, since a current path from the source electrode to the lead frame has a large cross-sectional area, the electric resistance can be reduced. However, as the plate is sealed with the resin forming the housing, heat generated from the semiconductor chip cannot be released when a particularly large amount of current is flown. Thus, illegal operations of the element, deformation, short-circuit, and the like may be caused by heat.
On the other hand, in a semiconductor device described in Japanese Patent Publication (Kokai) No. 2001-358259, a heat sink is provided on a semiconductor chip. The semiconductor chip is sealed in a housing. A source electrode disposed on a first principal surface of the semiconductor chip is connected to a first lead frame through a plurality of source wires. The gate electrode disposed on the first principal surface of the semiconductor chip is connected to a third lead frame through a single or a plurality of gate wires. A drain electrode disposed on the second principal surface of the semiconductor chip is connected to a second lead frame. Moreover, on the first principal surface of the semiconductor chip, the heat sink is provided. The heat sink has a surface exposed to the outside of the housing, so that the heat sink can release heat to the outside of the housing.
In the semiconductor device described in the Japanese Patent Publication (Kokai) No. 2001-358259, a heat sink is formed on the first principal surface of a semiconductor chip. Accordingly, heat generated from the semiconductor chip can be released. However a source electrode, through which a particularly large amount of current needs to flow, is connected to a lead frame by the plurality of wires. Therefore, a cross-sectional area of a current path from the source electrode to the lead frame is small, so that the electric resistance increases.